In recent years, liquid crystal display devices (LCDs) featuring thinness, lightweight, and low power consumption have become widespread, and have often been used as display units of mobile devices such as cellular phones (mobile phones), PDAs (personal digital assistants), and notebook PCs. Recently, however, a technology for supporting a larger screen and moving images of the liquid crystal display device has developed, so that implementation of large-screen display devices and large-screen liquid crystal television sets of a stationary type as well as those for mobile applications has become possible. As these liquid crystal display devices, the liquid crystal display devices with an active matrix driving system that enables high-resolution display are used. First, a typical configuration of the liquid crystal display device with the active matrix driving system will be outlined with reference to FIG. 20. A main configuration connected to one picture element in a liquid crystal display unit is schematically shown in the form of an equivalent circuit.
Generally, a display unit 960 in the liquid crystal device with the active matrix driving system is constituted from a substrate, an opposed substrate, and a structure with liquid crystals sealed therein between these opposed two substrates. In the semiconductor substrate, transparent pixel electrodes 964 and thin film transistors (TFTs) 963 (in the case of a color SXGA panel, for example, 1280×3 pixel rows×1024 pixel columns) are arranged in a matrix form. On the entire surface of the opposed substrate, one transparent electrode 966 is formed.
A TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale voltage corresponding to a video signal is applied to a pixel electrode 964. The transmissivity of a liquid crystal changes due to a difference in potential between each of the pixel electrodes 964 and the opposed substrate electrode 966, and the difference in potential is held at a liquid crystal capacitance 965 for a certain period, thereby displaying an image.
On the semiconductor substrate, data lines 962 for sending a plurality of levels of voltage (gray scale voltages) applied to the respective pixel electrodes 964 and scan lines 961 each for sending the scan signal are arranged in a matrix form (in the case of the color SXGA panel, 1280×3 data lines and 1024 scan lines are arranged). The scan lines 961 and the data lines 962 become large capacitive loads due to capacitances generated at mutual intersections and liquid crystal capacitances sandwiched with the opposed substrate electrode.
The scan signal is supplied to a scan line 961 by a gate driver 970, and supply of the gray scale voltage to each of the pixel electrodes 964 is performed from a data driver 980 through a data line 962.
Rewriting of data for one screen is performed in one frame period ( 1/60 seconds), and each pixel row (each line) is selected one by one for each scan line. The gray scale voltage is supplied from each data line within the period of the selection.
While the gate driver 970 should supply at least a binary scan signal, the data driver 980 needs to drive the data line by multi-levels of gray scale voltages corresponding to the number of gray scales. For this reason, as the buffer unit of the data driver 980, a differential amplifier that can perform voltage output with high accuracy is employed.
Further, in recent years, higher picture quality (creation of multiple colors) has been pursued, so that the demand for at least 260 thousand colors (6-bit video data for each of RGB), and further the demand for 16,800 thousand colors (8-bit video data for each of RGB) or more have increased.
For this reason, the data driver that outputs gray scale voltages corresponding to multi-bit video data is required to perform voltage output with an extremely high degree of accuracy. Further, the number of devices in a circuit unit that processes the video data has increased, and the chip area of a data driver LSI has increased, which have become a factor causing higher cost. This problem will be described below in detail.
FIG. 21 is a diagram showing a configuration of the data driver 980 in FIG. 20, and shows the pertinent portion of the data driver 980 in the form of blocks. Referring to FIG. 21, the data driver 980 includes a latch address selector 981, a latch 982, a gray scale voltage generation circuit 983, a plurality of decoders 984, and a plurality of buffer circuits 985.
The latch address selector 981 determines a data latch timing based on a clock signal CLK. The latch 982 latches digital video data based on the timing determined by the latch address selector 981, and outputs the latched data to each of the decoders 984 in unison in response to an STB signal (strobe signal). The gray scale voltage generation circuit 983 generates gray scale voltages with the number of gray scales corresponding to the video data. Each decoder 984 selects one of the gray scale voltages corresponding to the input data, for output. Each buffer circuit 985 receives the gray scale voltage output from the decoder 984, current amplifies the gray scale voltage, for output as an output voltage Vout.
When 6-bit video data is input, for example, the number of gray scales is 64. The gray scale voltage generation circuit 983 generates gray scale voltages at 64 levels. Each decoder 984 includes a circuit for selecting one of the gray scale voltages at 64 levels.
On the other hand, when 8-bit video data is supplied, the number of gray scales becomes 256. Thus, the gray scale voltage generation circuit 983 generates gray scale voltages at 256 levels. Each decoder 984 includes a circuit for selecting one of the gray scale voltages at 256 levels.
When multiple bits are used as described above, the circuit sizes of the gray scale voltage generation circuit 983 and the decoders 984 will increase. When an increase from six bits to eight bits is made, the circuit sizes become four times or larger. Accordingly, the chip area of the data driver LSI increases to bring about the higher cost due to the use of multiple bits.
On contrast therewith, there is proposed in Patent Document 1 (U.S. Pat. No. 6,246,351) an example of a technique for suppressing an increase in the chip area of the data driver LSI even if multiple bits are used. FIG. 22 is a diagram showing a configuration described in the Patent Document 1. Referring to FIG. 22, there is shown a differential amplifier in which a plurality of differential pairs 3110, 3120, 3130, and 3140 of a same polarity are connected to a common current mirror 3101, and these differential pairs are driven by individual current sources.
One of voltages Vin1 and Vin2 is supplied to each of the gates (non-inverting inputs) of N-channel MOS transistors 3111, 3121, 3131, and 3141 of the differential pairs 3110, 3120, 3130, and 3140, respectively, through a switch 3150, and an output voltage Vout is feedback connected to the gates (inverting inputs) of the transistors 3112, 3122, 3132, and 3142. According to this differential amplifier, a voltage obtained by internally dividing the voltage Vin1 and the voltage Vin2 at an arbitrary ratio according to a ratio between the number of inputs of the Vin1 and the number of inputs of the Vin2, supplied to the non-inverting inputs.
By using the differential amplifier in FIG. 22 as the buffer circuit in FIG. 21, the number of input gray scale power supplies can be reduced more greatly than the number of gray scale power supplies to be output.
When the differential amplifier of the configuration shown in FIG. 22 has four differential pairs as shown in the drawing, for example, four voltages obtained by internally dividing the Vin1 and the Vin2 by ratios of one to three, one to one, and three to one, respectively and the Vin2 can be output (four divided outputs). In other words, the number of gray scale power supply lines for input can be reduced more than the number of gray scales for output. Accordingly, the areas of the decoders 984 and the gray scale voltage generation circuit 983 in FIG. 21 can be reduced, so that the chip area can be reduced.
Recently, in addition of the use of multiple bits, the higher definition of the liquid crystal display device is very much remarkable, so that the enormous number of pixels such as an XGA (1024 pixels×768 lines), an SXGA (1280 pixels×1024 lines), and a UXGA (1600 pixels×1200 lines) must be driven. Then, with the higher definition, power consumption of the liquid crystal display device increases.
For this reason, power saving and voltage reduction have become very great challenges.
An example of a technique for reducing the power consumption of the data driver LSI is proposed in Patent Document 2 (JP Patent Kokai Publication No. JP-A-6-326529). FIG. 23 is a diagram showing a configuration described in the Patent Document 2. Referring to FIG. 23, this circuit includes a first differential pair 3210 and a second differential pair 3220. The first differential pair is constituted from N-ch transistors NM1 and NM2 with sources thereof connected in common to a constant current source. The second differential pair 3220 is constituted from P-ch transistors PM1 and PM2 with sources thereof connected in common to a constant current source. The pair of outputs of the first differential pair 3210 is connected to a high-potential power supply Vdd through a first load circuit (a current mirror circuit constituted from transistors PM3 and PM4). The pair of outputs of the second differential pair 3220 is connected to a low-potential power supply VSS through a second load circuit (a current mirror circuit constituted from transistors NM3 and NM4). The output terminal of the first load circuit (the drain of a PMOS transistor PM5 that constitutes the output terminal of a cascode current mirror) is connected to the gate of a PMOS transistor PM10. The source of the PMOS transistor PM10 is connected to the power supply Vdd, and the drain of the PMOS transistor PM10 is connected to the output terminal of the circuit. The output terminal of the second load circuit (the drain of an NMOS transistor NM5 that constitutes the output terminal of a cascode current mirror) is connected to the gate of an NMOS transistor NM10. The source of the NMOS transistor NM10 is connected to the power supply Vss and the drain of the NMOS transistor NM10 is connected to the output terminal. An output terminal Vout is feedback connected to the inverting input of the differential pairs, and a capacitor for preventing oscillation is connected to the output terminal Vout. Incidentally, reference numerals 3231 and 3232 denote floating current sources, for example. A differential amplifier of the configuration described above is the differential amplifier that can perform output over the full range of supplied voltages. Thus, such a differential amplifier 3200 is referred to as a “Rail-to-Rail amplifier (or also referred to as a “Rail-to-Rail Op Amp”).
When the Rail-to-Rail amplifier as described above is employed as the buffer circuit, the range of supply voltages that is necessary for operating the amplifier is the same as the voltage range of liquid crystal elements to be driven. Thus, voltage reduction can be achieved, so that power saving can be implemented.
[Patent Document 1]
U.S. Pat. No. 6,246,351
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-6-326529